Business introduction
    It is difficult to analyze and find signal integrity problems on an existing board, even though the problems have been found, lots of time and high cost will be needed to solve them. The most effective way is to check, find, and eliminate or reduce signal integrity problems during circuit design before physical design completed, which requires designers to do simulation analysis on circuit parameters with the assistance of EDA tools so as to find problems at an early stage, shorten RD cycle, and reduce RD costs. Besides, it will improve designers’ confidence.

    Hampoo has a perfect simulation design flow and solutions on SI problems. Based on SI design and timing requirements, signal integrity simulation before routing can help designers choose components and parts, adjust component and parts placement, plan system clock network and confirm termipoint strategy and topology structure of key networks. Simulation after routing can be used to evaluate if the reflection, ringing, over swing, crosstalk, timing and other parameters of routing match design requirements, so as to help them find potential SI problems and improve design reliability.
Multi-load topology simulation
    Characteristics of multi-load topology:overload, remote distance, non-equivalence load , serious reflection, and asynchronous sequence or public clock sequence
    Typical bus: Local bus and PCI, etc.
    Contents of SI analysis: parts layout, topology optimization, matching plan, load waveform, and time sequence analysis.
DDR1/2/3 Memory bus simulation
    Memory bus: DDR1, DDR2, DDR3, DDR4, QDR, TCAM, and DIMM
    Characteristics of Memory bus: heavy load, dense routing, and high time sequence requirements
    Contents of simulation analysis: parts layout, topology design, matching plan, waveform analysis, and time sequence analysis
High-speed serial bus simulation

    Characteristics of SERDES simulated bus: point-to-point transmission, remote distance, great loss, and being easily affected by reflection and crosstalk

    Maximum design speed and length:
    2008 Infiniband QDR 10Gbps 64cm
    2011年10Gbase-KR 10.3125Gbps 70cm
    2012 Infiniband FDR 14Gbs 100cm
    2013年CEI-25G-VSR 25Gbps 10.6cm

    Contents of simulation analysis: material selection, optimization of lamination, via-hole, connector, and coupling capacitance parameters, loss parameter extraction, eye pattern analysis, and jitter

    Methods for channel performance analysis:
    frequency domain analysis, TDR analysis, Spice analysis, and IBIS-AMI Channel analysis
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